The main goal of a power distribution network is to reduce the inductance between connected components. This is most important for whatever plane you’re using as a reference (e.g. “ground”, “vref”, or “return”) because the voltage on that net is used as a reference for the voltages on your signals. (E.g. a TTL signal’s VIL/VIH thresholds are referenced to the chip’s GND pin, not VCC.) Resistance is actually not that important in most PCB applications because the inductance component of the total impedance dominates. (On an IC chip, though, this is reversed: resistance is the dominant part of impedance.)
Please bear in mind that these issues are most important for high-speed (>1 MHz) circuits.
Reference Plane as Lumped Node
The first thing to check is if your reference plane can be considered a lumped node, as opposed to a transmission line. If the rise time of your signal is greater than the time light needs to cross from one edge of the board to the other and back (in copper; a good rule of thumb is 8 inches per nanosecond), then you can consider the reference plane to be a lumped element, and the distance from load to decoupling capacitor does not matter. This is an important determination to make, since it affects your placement strategy for power vias and capacitors.
If the plane dimensions are larger, then you not only need to spread decoupling capacitors around, you also need more of them and the capacitors need to be within the rise-time distance of the load they are decoupling.
Continuing our efforts to minimize inductance, if the plane is a lumped element, then the inductance between part and plane becomes dominant. Consider C19 in your first example. The inductance seen from the plane to the chip is directly related to the area enclosed by the tracks. In other words, follow the path from the power plane, to the chip, then back out the ground pin to the ground plane, finally closing the loop back to the power via. Minimizing this area is your goal, as less inductance means more bandwidth before inductance becomes dominant over decoupling capacitance. Remember, the length of the via from surface to plane is part of the path; keeping reference planes near the surfaces helps a lot. It’s not uncommon in 6 or more layer boards for the first and last inner layers to both be reference planes.
So while you have a pretty small inductance to start with (I’m guessing 10-20 nH), it can be reduced by giving the IC its own set of vias: given your via size, one via next to pin 97 and another near pin 95 would cut inductance down to 3 nH or so. If you can afford it, smaller vias would help here. (Though, honestly, since your part is an LQFP instead of a BGA, this may not help a huge amount because the lead frame in the package could be contributing 10 nH all by itself. Or maybe it’s not that much because of …)
The lines and vias leading to a load or capacitor don’t exist in a vacuum. If there is a supply line, there needs to be a return line. Since these are wires with currents flowing through them, they generate magnetic fields, and if they are close enough to each other, they create mutual inductance. This can be either harmful (when it increases total inductance) or beneficial (when it decreases total inductance).
If the currents in each of the parallel wires (I say “wire” to include both trace and via) are going in the same direction, then the mutual inductance adds to the self-inductance, increasing total inductance. If the currents in each wire are going in opposite directions, then the mutual inductance subtracts from the self-inductance, decreasing the total. This effect gets stronger as the distance between the wires goes down.
Therefore, a pair of wires going to the same plane should be far apart (rule of thumb: greater than twice the distance from surface to plane; assume the PCB thickness if you don’t have your stackup figured out yet) to reduce total inductance. A pair of wires going to different planes, such as every example you have posted, should be as close together as possible.
Since inductance is dominant, and (for high-speed signals) is determined by the path the current takes through the net, plane cuts should be avoided, especially if there are signals crossing that cut, since the return current (which prefers to follow a path directly under the signal trace to minimize loop area and thus inductance) has to make a large detour, increasing inductance.
One way to mitigate the inductance created by cuts is to have a local plane which can be used to jump over the cut. In this case, several vias should be used to minimize the length of the return current path, however, since these are vias which go to the same plane, and thus have current flow in the same direction, they should not be placed close to each other, but should be at least two plane distances or so apart.
Care should be taken, though, with signal traces that are long enough to be transmission lines (i.e. over one rise or fall time in length, whichever is shorter), because a ground fill near the trace will change the impedance of that trace, causing a reflection (i.e. overshoot, undershoot, or ringing). This is most noticeable in gigabit-speed signals.
Out of time
I’d go into how the “one 0.1 uF capacitor per power pin” strategy is counterproductive with modern designs that can have tens of power pins per part, but I really have to go to work now. Details are in the BeTheSignal and Altera PDN links below.
- Move decoupling capacitor vias closer together, if those vias go to different planes.
- Putting the via in the pad is the best option, if you can afford it (you need to fill the via and plate the pad over the fill, which adds a day or two to fabrication and costs more money). Second best is to put the two vias on the same side of the cap, as close as possible to each other and the capacitor. An additional set of vias can be placed on the opposite side of the capacitor to cut the inductance in half, but make sure that the two via groups are at least a board thickness (or two plane distances) apart.
- Give the IC its own vias to power and ground, keeping opposing-net vias near each other and same-net vias farther apart. These vias can be shared with decoupling capacitors, but it is better to have more plane vias than to lengthen traces to plane vias. (My usual layout technique is to place the load, then place the power and ground vias, and finally place a decoupling capacitor on the opposite side of the board if there’s room. (If there’s no room, the capacitor moves, not the vias!)
- Minimize the longest dimension of each reference plane to minimize inductance and allow the simpler lumped-element model for your plane. Plane cuts should be minimized, and local planes can be used to mitigate them.
- Henry Ott, Electromagnetic Compatibility Engineering
- Altera’s Power Distribution Network design tool and app note — These are focused on Altera products, but the basic strategies are relevant to any high-speed digital design. The PDN tool is great for calculating plane impedance given physical parameters and decoupling capacitors. Puts the “one 0.1 uF cap per power pin” myth to bed by showing you what really happens.
– Mike DeSimone